So this combination can be thought of as a gated D latch with latched input gates. The trick of this clever circuit solution (7474 positive-edge triggered D latch) is to latch the inputs of an RS latch by RS latches. There are two "1s" at the inputs of the MAIN LATCH so it is released and begins holding its contents.ģ. When the Clock is low again, the NAND 2 and NAND 3 outputs are forced to be high.
![neg edge triggered flip flop neg edge triggered flip flop](https://i.ytimg.com/vi/X-DFxfwzUJ8/maxresdefault.jpg)
So, if Data goes high until Clock is high, this will not change the latch states.Ĭlock = 0. that is forced to stay in this state (Q = "1") until the Clock is high.Īnd here is the key point of this circuit solution - from now on, the input latches can no longer be controlled by the input D. The data from its outputs is stored in the MAIN LATCH. and the BIG LATCH is set to the state corresponding to the input signal Data (S LATCH - "1", R LATCH - "0"). The positive feedbacks - two local and one global, begin acting. When the clock signal goes high (logical "1"), NAND 2 and NAND 3 are enabled and the input latches are unblocked. and also, the BIG LATCH consisting of them is blocked (there are no positive feedbacks).Ĭlock = 1. and this is the neutral input combination for the MAIN LATCH allowing it to hold undisturbed the previous Data. As the Clock is low, there are logical "0s" at the R input of the S LATCH (NAND 2) and at the S input of the R LATCH (NAND 3). Also, for completeness, assume some value of the Data input, e.g., "0".Ĭlock = 0. What does all that mean? What is the sense of this additional positive feedback as they have such?Ģ. The Data signal is inserted in the global loop so it acts as a sole input to the big latch. as they say, they are "cross-coupled" like the single RS LATCH where two NANDs are cross-coupled. In other words, both input latches are connected in a "global" positive feedback loop. Then we see something else interesting and quite odd - the Q output of the R LATCH is connected to the R input of the S LATCH, and then the Q output of the S LATCH is connected to the R input of the R LATCH. So, our first conclusion is that we see an RS latch wich inputs are latched by the same RS latches. The S LATCH (NAND 1 and NAND 2) is inserted before the S input and the R LATCH (NAND 3 and NAND 4) - before the R input of the MAIN LATCH. The other two latches are connected to its inputs. As we can see, there is one MAIN LATCH (on the right) assembled by NAND 5 and NAND 6. But how are they connected to each other?ġ. As OP have figured out, there are three \$R\neg\$ \$S\neg\$ latches in total (for simplicity, I will name them "RS latches"). The situation is difficult but intriguing - there is an unknown circuit in front of us and we begin looking for something familiar in it. I think there is always an intuitive way to understand a circuit.